The conventional techniques for manufacturing the high-voltage or power devices in HVICs or PICs use dielectric isolation (DI), p-n junction isolation (JI) and self isolation (SI). Among these three techniques, the isolation performance of DI is the best, and the JI is better than SI, whereas the cost of SI is the lowest, and the cost of DI is the highest.
As shown in FIG. 1, a conventional HVIC includes four portions: a low-voltage control circuit, a low-side driver connected to ground (substrate), a high-voltage level shifter and a high-side driver. It can be seen from FIG. 1 that a common terminal of the high-side driver is connected with a middle terminal of an output of a totem pole, and the potential of the middle terminal can vary from the voltage of the ground (substrate) up to that of a high-voltage bus. That is to say, this kind of power integrated circuit (or HVICs) has a common floating voltage terminal which is used as a low voltage terminal in the high-side driver, and other circuits use the substrate to be a common voltage terminal. In the conventional technique for high-voltage integrated circuits, the above-mentioned two kinds of circuits used to be formed on two chips, separately.
B. Murari et al. describe a BCD technique in "Smart Power ICs Technologies and Applications (Springer-veriag, Berlin, Heidelberg, New York, 1995)", which can be used to integrate the two kinds of circuits in a single chip. The BCD techniques, however, must use Di and JI technique so that its process is not technologically compatible with conventional CMOS or BiCMOS technology. It also needs a large area of a chip. Therefore, the cost of BCD technique is quite high. In the present technical field, an important task is to seek a method to fabricate the two kinds of circuits in a single chip without using DI and JI techniques and technologically compatible with conventional CMOS or BiCMOS technology so that the cost of the HVIC can be reduced. Moreover, as shown in FIG. 1, the high-voltage integrated circuit is used to drive at least two high-voltage devices connected in series, one of them is a high-side MOST and another is a low-side MOST. The two devices connected in series form a totem pole if one is an n-MOST and the other is also an n-MOST. The two devices connected in series form a CMOS if one is an n-MOST and the other is a p-MOST. Normally, the high-voltage power MOSTs in FIG. 1 are discrete devices, not Integrated on the chip. Therefore, the protection circuits of the power devices are complicated.
The present inventor has disclosed a technique for manufacturing a surface sustaining region in semiconductor device in U.S. Pat. No. 5,726,469 (X. B. Chen, "Surface Voltage Sustaining Structure for Semiconductor Device"). By using the technique of U.S. Pat. No. 5,726,469, a power device having excellent electrical performance can be realized without using DI and JI technique. In addition, since the implementation of the surface voltage sustaining structure of U.S. Pat. No. 5,726,469 is flexible, and may be technologically compatible with micron or sub-micron CMOS or BiCMOS technology, thereby the cost for manufacturing power device (or high voltage device) in power integrated circuits by using this technique is much lower than that by using DI and JI technology. FIG. 2 shows an example of manufacturing a high voltage diode by using the technique of U.S. Pat. No. 5,726,469. In this figure, two p.sup.+ -zones 3 and 4 cover on an n.sup.+ -region 2 formed on a p.sup.- -substrate 1, a cathode K is located in the center of the n.sup.+ -region 2, and an anode A is connected with the substrate 1 through a p.sup.+ -zone 5. Obviously, in this method, the anode A must have a potential being the same as that of the substrate, and can not have a varying (or floating) high voltage relative to the substrate. That is to say, this kind of surface voltage sustaining structure can only apply to a device having a low voltage terminal connected to the substrate and a high voltage terminal relative to the substrate.
As above-mentioned, the power integrated circuit comprises not only device(s) with the substrate being a low voltage terminal (this kind of device is called as low-side device hereafter), but also high voltage device(s) with a varying (or floating) voltage at its low voltage terminal (this kind of device is called as high-side device hereafter), and the floating voltage may be very high. A high-side n-MOST device shown in FIG. 3 belongs to this kind of device, which can not be manufactured by means of the technique of U.S. Pat. No. 5,726,469. Furthermore, in a semiconductor power integrated circuit, some low voltage integrated circuit are often needed. This low voltage circuit has a common terminal connected to a floating voltage terminal of a high-voltage device having the floating voltage terminal. The block shown in FIG. 3 is this kind of low-voltage integrated circuit. In this kind of circuits, many devices are formed in a "tub", which has a function like a "substrate". There is a floating voltage between such a "substrate" and the substrate of a chip. The tub has a floating voltage from zero to very high, but the performance of those devices formed therein should not be affected by the floating voltage. One of the conventional methods for manufacturing the above mentioned integrated circuit is to form the high-side n-MOST on a chip (a discrete device) while the tub having a floating voltage terminal (Floating High-Voltage "TUB") is formed on another chip. If the low-side device sustains a voltage higher than 500V, and a current larger than 1 A, then still another discrete device is used. Another conventional method for manufacturing the integrated circuit is to form said three kinds of devices on a single chip with SI and JI technology. In this way, the disadvantages are high cost and large consumption of the chip area.
As shown in FIG. 4, the technique of U.S. Pat. No. 5,726,469 may also be used to manufacture the tub shown in FIG. 3. Compared with FIG. 2, the difference of FIG. 4 is that there is a p-zone 12, around the center. A frame surrounded by the dashed lines indicates a tub region which is not depleted when a breakdown voltage is applied at the floating voltage terminal SH. An examples of usage of the tub region is that low-voltage p-MOSTs can be made in the undepleted area of the n.sup.+ -region 2, and low-voltage n-MOSTs can be made on the undepleted area of the p-zone 12. The manufacturing method is the same as that for implementation of the conventional integrated circuit devices in n-"substrate" (here is the n.sup.+ -region 2) and p-well (here is the p-zone 12). However, the above method still has the disadvantage that the high-side high-voltage device having a floating voltage terminal can not be made on the same chip.